Experiences with Life-cycle Aware Computer Architecture

John Oliver
California Polytechnic State University, San Luis Obispo, California, USA.
E-mail: jyoliver@ucdavis.edu

Roland Geyer, Alan Savage and Frederic T. Chong
University of California, Santa Barbara, California, USA

Rajeevan Amirtharajah and Venkatesh Akella
University of California, Davis, California, USA

Abstract:
The dark side of Moore’s Law is our society’s insatiable need to constantly upgrade our computing devices. As a result, the typical processor is only used for a fraction of it’s expected lifetime, despite the immense cost to produce a processor. While the rapid advance of technology makes silicon obsolete in a few years, we propose that chips should be reused for less demanding computing tasks. This re-use strategy creates a food chain of computing devices which amortizes the energy required to build processors over several computing generations.
This paper is structured into two parts. First, we describe a proposed a processor re-use strategy, showing that processor re-use makes sense for low-power, embedded processors. These re-usable processors occupy a design space that requires us to implement flexible and reliable processors. The second part of this paper describes student efforts centered around re-usable processors at California Polytechnic State University, San Luis Obispo as well as the University of California, Santa Barbara.

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